Intel "Panther Lake - H" mobile processor details revealed, featuring a modular chip design

IT House March 8 News, according to TechPower Up’s report yesterday, the semiconductor deep analysis platform Kurnal Insights recently released a Die-Shot photo of Intel’s “Panther Lake-H” mobile processor.

▲ Image source: Kurnal Insights, same below

From the photo, we can see that the “Panther Lake-H” processor uses a modular chip design, with an overall appearance similar to the previous Arrow Lake-H and Meteor Lake products. However, this layout is more similar to Lunar Lake, with the SoC Tile containing CPU cores, NPU, and memory controllers, the Graphics Tile housing the integrated graphics unit, and the I/O Tile responsible for various platform I/O components.

The SoC Tile is manufactured using Intel’s 18A process technology, while in mainstream models, the Graphics Tile contains only 4 Xe cores and is built with Intel 3 process, and the I/O Tile uses the previous generation N6 process. In comparison, the Panther Lake-U processor’s Graphics Tile has 12 Xe cores and is manufactured with TSMC’s N3E process.

Specifically, Panther Lake-H consists of four modules (Tiles): the base Tile, made with a 22nm process, acts as an intermediary layer providing high-density connections for the stacked Tiles above; the other three modules are Compute Tile, Graphics Tile, and I/O Tile. Although they are tightly integrated into an irregular shape, Intel uses Filler Tile structures to make the final chip a regular rectangle.

The Compute Tile measures 14.32 mm × 8.04 mm (about 115 mm²) and contains 6P + 8E + 4LPE cores. The main compute complex includes 6 performance cores (P cores) based on Cougar Cove and 2 efficiency cores (E cores) based on Darkmont, connected via Ringbus, sharing 18MB of L3 cache.

Additionally, each P core has 3MB of dedicated L2 cache; the two E cores share 4MB of L2 cache.

In terms of frequency, the P cores can reach up to 5.10 GHz, the E cores up to 3.80 GHz, and the low-power E cores have a lower base frequency with a maximum of 3.70 GHz.

Besides CPU cores, the Compute Tile also includes a memory controller, 8MB of memory-side cache, supporting dual-channel DDR5 and LPDDR5X with a maximum speed of 9600 MT/s. The Intel NPU 5 is also part of this, containing three neural compute engines, each with 1.5MB cache, totaling 4.5MB, with the remaining transistors possibly allocated to media engines and other functions.

Next, we see that the Graphics Tile measures 8.14 mm × 6.78 mm (about 55.18 mm²), containing 12 Xe cores and 16MB of L2 cache, based on the Xe3 Celestial architecture.

Finally, the elongated I/O Tile measures 12.44 mm × 4 mm (about 49.76 mm²), containing PCIe root hubs and Thunderbolt 5 (or USB4 v2) controllers, providing 4 PCIe 5.0 lanes, 8 PCIe 4.0 lanes, and 2 Thunderbolt 5 interfaces. It also integrates Wi-Fi 7 and Bluetooth 5.4 controllers.

IT House note: Die-Shot refers to a microscopic photograph or layout diagram of the physical structure inside the chip, used to analyze the chip’s specific design and area distribution.